Regviz

Espressif Systems /ESP32-P4 /HP_SYS_CLKRST /HP_RST_EN0

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as HP_RST_EN0

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-P4/HP_SYS_CLKRST/HP_RST_EN0#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (REG_RST_EN_CORECTRL)REG_RST_EN_CORECTRL 0 (REG_RST_EN_PVT_TOP)REG_RST_EN_PVT_TOP 0 (REG_RST_EN_PVT_PERI_GROUP1)REG_RST_EN_PVT_PERI_GROUP1 0 (REG_RST_EN_PVT_PERI_GROUP2)REG_RST_EN_PVT_PERI_GROUP2 0 (REG_RST_EN_PVT_PERI_GROUP3)REG_RST_EN_PVT_PERI_GROUP3 0 (REG_RST_EN_PVT_PERI_GROUP4)REG_RST_EN_PVT_PERI_GROUP4 0 (REG_RST_EN_REGDMA)REG_RST_EN_REGDMA 0 (REG_RST_EN_CORE0_GLOBAL)REG_RST_EN_CORE0_GLOBAL 0 (REG_RST_EN_CORE1_GLOBAL)REG_RST_EN_CORE1_GLOBAL 0 (REG_RST_EN_CORETRACE0)REG_RST_EN_CORETRACE0 0 (REG_RST_EN_CORETRACE1)REG_RST_EN_CORETRACE1 0 (REG_RST_EN_HP_TCM)REG_RST_EN_HP_TCM 0 (REG_RST_EN_HP_CACHE)REG_RST_EN_HP_CACHE 0 (REG_RST_EN_L1_I0_CACHE)REG_RST_EN_L1_I0_CACHE 0 (REG_RST_EN_L1_I1_CACHE)REG_RST_EN_L1_I1_CACHE 0 (REG_RST_EN_L1_D_CACHE)REG_RST_EN_L1_D_CACHE 0 (REG_RST_EN_L2_CACHE)REG_RST_EN_L2_CACHE 0 (REG_RST_EN_L2_MEM)REG_RST_EN_L2_MEM 0 (REG_RST_EN_L2MEMMON)REG_RST_EN_L2MEMMON 0 (REG_RST_EN_TCMMON)REG_RST_EN_TCMMON 0 (REG_RST_EN_PVT_APB)REG_RST_EN_PVT_APB 0 (REG_RST_EN_GDMA)REG_RST_EN_GDMA 0 (REG_RST_EN_MSPI_AXI)REG_RST_EN_MSPI_AXI 0 (REG_RST_EN_DUAL_MSPI_AXI)REG_RST_EN_DUAL_MSPI_AXI 0 (REG_RST_EN_MSPI_APB)REG_RST_EN_MSPI_APB 0 (REG_RST_EN_DUAL_MSPI_APB)REG_RST_EN_DUAL_MSPI_APB 0 (REG_RST_EN_DSI_BRG)REG_RST_EN_DSI_BRG 0 (REG_RST_EN_CSI_HOST)REG_RST_EN_CSI_HOST 0 (REG_RST_EN_CSI_BRG)REG_RST_EN_CSI_BRG 0 (REG_RST_EN_ISP)REG_RST_EN_ISP 0 (REG_RST_EN_JPEG)REG_RST_EN_JPEG 0 (REG_RST_EN_DMA2D)REG_RST_EN_DMA2D

Description

Reserved

Fields

REG_RST_EN_CORECTRL

Reserved
REG_RST_EN_PVT_TOP

Reserved
REG_RST_EN_PVT_PERI_GROUP1

Reserved
REG_RST_EN_PVT_PERI_GROUP2

Reserved
REG_RST_EN_PVT_PERI_GROUP3

Reserved
REG_RST_EN_PVT_PERI_GROUP4

Reserved
REG_RST_EN_REGDMA

Reserved
REG_RST_EN_CORE0_GLOBAL

Reserved
REG_RST_EN_CORE1_GLOBAL

Reserved
REG_RST_EN_CORETRACE0

Reserved
REG_RST_EN_CORETRACE1

Reserved
REG_RST_EN_HP_TCM

Reserved
REG_RST_EN_HP_CACHE

Reserved
REG_RST_EN_L1_I0_CACHE

Reserved
REG_RST_EN_L1_I1_CACHE

Reserved
REG_RST_EN_L1_D_CACHE

Reserved
REG_RST_EN_L2_CACHE

Reserved
REG_RST_EN_L2_MEM

Reserved
REG_RST_EN_L2MEMMON

Reserved
REG_RST_EN_TCMMON

Reserved
REG_RST_EN_PVT_APB

Reserved
REG_RST_EN_GDMA

Reserved
REG_RST_EN_MSPI_AXI

Reserved
REG_RST_EN_DUAL_MSPI_AXI

Reserved
REG_RST_EN_MSPI_APB

Reserved
REG_RST_EN_DUAL_MSPI_APB

Reserved
REG_RST_EN_DSI_BRG

Reserved
REG_RST_EN_CSI_HOST

Reserved
REG_RST_EN_CSI_BRG

Reserved
REG_RST_EN_ISP

Reserved
REG_RST_EN_JPEG

Reserved
REG_RST_EN_DMA2D

Reserved

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data